In a wireless communication apparatus, an RF circuit is formed of an analog circuit, and a baseband circuit is formed of a digital circuit in related art. An analog circuit occupies a large area and consumes a large amount of electric power. To address the problems, an RF circuit formed of a digital circuit has been studied, and an ADPLL (all digital phase locked loop) circuit corresponding to a PLL (phase locked loop) circuit, which plays an important role in processing an RF signal, has been proposed.
In an ADPLL circuit, a challenge is increasing the resolution of a TDC (time-to-digital converter) circuit that detects phase difference between two different clocks, that is, time difference between logical value rising edges of two pulse signals, and expresses the difference in a digital value.
The time difference between logical value rising edges of two pulse signals is detected as follows: First, one of the pulse signals is input to a delay circuit formed of a plurality of logic circuits connected in series so that the pulse signal propagates through the delay circuit. The other pulse signal is also input with time difference to another delay circuit formed of logic circuits connected in series so that the pulse signal propagates through the delay circuit. It is noted that each of the logic circuits in the latter delay circuit produces a signal delay period shorter than that produced in each of the logic circuits in the former delay circuit. The time difference described above may be determined by locating the logic circuits where the rising edge of the one pulse signal propagating through the former delay circuit coincides with the rising edge of the other pulse signal propagating through the latter delay circuit, because the time difference is equal to the product of the following two values: one is the difference between the signal delay period produced in the logic circuit through which the one pulse signal propagates and the signal delay period produced in the logic circuit through which the other pulse signal propagates, and the other is the number of logic circuits counted from the first one to the one where the rising edges coincides with each other.
In a TDC circuit, when series-connected logic circuits are used to form each delay circuit through which two pulse signals propagate so that the time difference therebetween is detected, large-scale delay circuits are requested.
To reduce the scale of the delay circuits, each of the delay circuits is formed by connecting an odd number of logic circuits each of which outputs an inverted logical value to form a loop so that a pulse signal propagates continuously (see National Publication of International Patent Application No. 2005-521059). When loop-shaped delay circuits are each formed of a small number of logic circuits each of which outputs an inverted logical value, the product of two values, one is the difference between the pulse cycle of an oscillatory clock produced by one pulse signal in one of the loop-shaped delay circuits and the pulse cycle of an oscillatory clock produced by the other pulse signal in the other loop-shaped delay circuit, and the other is the clock count at the time when the rising edges of the two oscillatory clocks coincide with each other, is equal to the time difference between the time when the one pulse signal is input and the time when the other pulse signal is input.
The difference in cycle between the oscillatory clocks is formed by changing the signal delay periods produced in the loop-shaped delay circuits because the cycle of each of the oscillatory clocks is determined in accordance with the sum of signal delay periods produced in the plurality of delay circuits. It is therefore difficult to reduce the difference in cycle between the oscillatory clocks unless the change in signal delay period is very small.
Further, since a rising edge of one oscillatory clock is used to detect a rising edge of the other oscillatory clock, the difference in cycle between the oscillatory clocks may not be smaller than the reaction time of a flip-flop circuit. Since the time difference between input signals is detected based on the time difference in cycle between the two oscillatory clocks, the detection precision is not improved.
The reason why rising edges of the two oscillatory clocks are used to detect the time difference between the input signals follows: In each loop-shaped delay circuit in which an oscillatory clock signal is produced, look at a single logic circuit that outputs an inverted logical value (inverter, for example). Since the loop-shaped delay circuit is formed of an odd number of inverters, the logical value of the signal output from the inverter of interest keeps rising and falling. The period from a rising edge of the logical value to a falling edge thereof is, however, not always one-half a single cycle. In this case, the difference between rising edges of the two oscillatory clocks may not be detected based on a rising edge of one of the oscillatory clocks and a falling edge of the other oscillatory clock.
As described above, it is difficult to improve the resolution of a TDC circuit for detecting the time difference by using delay circuits each of which is formed by connecting logic circuits each of which outputs an inverted logical value to form a loop.